C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 143

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF2H
R/W
Bit7
TF2H: Timer 2 High Byte Overflow Flag
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will
occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is enabled, set-
ting this bit causes the CPU to vector to the Timer 2 interrupt service routine. TF2H is not automati-
cally cleared by hardware and must be cleared by software.
TF2L: Timer 2 Low Byte Overflow Flag
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. When this bit is set, an
interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled. TF2L will set when
the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hard-
ware.
TF2LEN: Timer 2 Low Byte Interrupt Enable.
This bit enables/disables Timer 2 Low Byte interrupts. If TF2LEN is set and Timer 2 interrupts are
enabled, an interrupt will be generated when the low byte of Timer 2 overflows. This bit should be
cleared when operating Timer 2 in 16-bit mode.
0: Timer 2 Low Byte interrupts disabled.
1: Timer 2 Low Byte interrupts enabled.
UNUSED. Read = 0b. Write = don’t care.
T2SPLIT: Timer 2 Split Mode Enable
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2. In 8-bit mode, this bit enables/disables TH2 only; TL2 is always
enabled in this mode.
0: Timer 2 disabled.
1: Timer 2 enabled.
UNUSED. Read = 0b. Write = don’t care.
T2XCLK: Timer 2 External Clock Select
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit selects the
external oscillator clock source for both timer bytes. However, the Timer 2 Clock Select bits (T2MH
and T2ML in register CKCON) may still be used to select between the external clock and the system
clock for either timer.
0: Timer 2 external clock selection is the system clock divided by 12.
1: Timer 2 external clock selection is the external clock divided by 8. Note that the external oscillator
source divided by 8 is synchronized with the system clock.
TF2L
R/W
Bit6
Figure 15.13. TMR2CN: Timer 2 Control Register
TF2LEN
R/W
Bit5
R/W
Bit4
-
T2SPLIT
R/W
Bit3
Rev. 2.3
TR2
R/W
Bit2
C8051F300/1/2/3/4/5
R/W
Bit1
-
(bit addressable)
T2XCLK
R/W
Bit0
SFR Address:
00000000
Reset Value
0xC8
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