C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 31

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

5.
The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as AMUX0)
with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8-bit successive-
approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram
in Figure 5.1). The AMUX0, PGA, data conversion modes, and window detector are all configurable under software
control via the Special Function Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential
modes, and may be configured to measure any Port pin, the Temperature Sensor output, or VDD with respect to any
Port pin or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register
(ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Sensor
Temp
ADC0 (8-BIT ADC, C8051F300/2)
GND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
AMUX0
10-to-1
Figure 5.1. ADC0 Functional Block Diagram
AMUX
AMUX
9-to-1
X
+
-
AMX0SL
VDD
Rev. 2.3
ADC0CF
ADC
VDD
C8051F300/1/2/3/4/5
8-Bit
SAR
ADC0GT
ADC0LT
ADC0CN
Conversion
Start
16
8
000
001
010
011
1xx
AD0WINT
Comb.
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Logic
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