C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 77

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state,
the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data mem-
ory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is
reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled during and after
the reset. For VDD Monitor and power-on resets, the /RST pin is driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator.
Refer to
The Watchdog Timer is enabled with the system clock divided by 12 as its clock source
Timer Mode” on page 156
execution begins at location 0x0000.
XTAL1
XTAL2
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Section “11. Oscillators” on page 89
RESET SOURCES
Oscillator
Oscillator
External
Internal
Drive
P0.x
P0.y
details the use of the Watchdog Timer). Once the system clock source is stable, program
Clock Select
System
Clock
Comparator 0
+
-
Detector
Missing
Clock
(one-
shot)
Figure 9.1. Reset Sources
Microcontroller
EN
Extended Interrupt
C0RSEF
CIP-51
for information on selecting and configuring the system clock source.
Core
Handler
VDD
WDT
PCA
EN
Supply
Monitor
+
-
System Reset
Rev. 2.3
Enable
Power On
Reset
C8051F300/1/2/3/4/5
(Software Reset)
SWRSF
'0'
Operation
FLASH
Illegal
(Section “16.3. Watchdog
(wired-OR)
Reset
Funnel
/RST
77