C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 80
![IC 8051 MCU 8K FLASH 11MLP](/photos/16/12/161294/c8051f300_sml.jpg)
C8051F302
Manufacturer Part Number
C8051F302
Description
IC 8051 MCU 8K FLASH 11MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Specifications of C8051F302
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F302-GMR
Manufacturer:
SiliconL
Quantity:
3 000
Company:
Part Number:
C8051F302-GMR
Manufacturer:
SILICON
Quantity:
5 000
Part Number:
C8051F302-GMR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
C8051F300/1/2/3/4/5
The FERROR bit (RSTSRC.6) is set following a FLASH error reset. The state of the /RST pin is unaffected by this
reset.
9.8.
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a
software forced reset. The state of the /RST pin is unaffected by this reset.
80
-40°C to +85°C unless otherwise specified.
Missing Clock Detector Timeout
VDD POR Threshold (V
Minimum /RST Low Time to
/RST Input Leakage Current
/RST Output Low Voltage
/RST Input High Voltage
Generate a System Reset
/RST Input Low Voltage
Software Reset
Reset Time Delay
PARAMETER
RST
C8051F305
Table 9.1. User Code Space Address Limits
Device
Table 9.2. Reset Electrical Characteristics
)
source and code execution at location
I
OL
Delay between release of any reset
Time from last system clock rising
= 8.5 mA, VDD = 2.7 V to 3.6 V
edge to reset initiation
CONDITIONS
/RST = 0.0 V
0x0000
User Code Space Address Limit
Rev. 2.3
0x07FF
VDD
MIN
0.7 x
2.40
100
5.0
15
TYP
2.55
220
25
MAX
VDD
0.3 x
2.70
500
0.6
40
UNITS
µA
µs
µs
µs
V
V
V