C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 157

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset
value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L
overflow occurs, depending on the value of the PCA0L when the update is performed. The total offset is then given
(in PCA clocks) by Equation 16.4, where PCA0L is the value of the PCA0L register at the time of the update.
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and PCA0H. Soft-
ware may force a WDT reset by writing a ‘1’ to the CCF2 flag (PCA0CN.2) while the WDT is enabled.
16.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
•
•
•
•
•
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The Watchdog Timer is
enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the WDT cannot be
disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12,
PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 16.4, this results in a WDT timeout inter-
val of 3072 system clock cycles. Table 16.3 lists some example timeout intervals for typical system clocks, assuming
SYSCLK / 12 as the PCA clock source.
Disable the WDT by writing a ‘0’ to the WDTE bit.
Select the desired PCA clock source (with the CPS2-CPS0 bits).
Load PCA0CPL2 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle mode).
Enable the WDT by setting the WDTE bit to ‘1’.
†
time.
††
Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L value of 0x00 at the update
Internal oscillator reset frequency.
System Clock (Hz)
Equation 16.4. Watchdog Timer Offset in PCA Clocks
Offset
3,060,000
3,060,000
3,060,000
Table 16.3. Watchdog Timer Timeout Intervals
24,500,000
24,500,000
24,500,000
18,432,000
18,432,000
18,432,000
11,059,200
11,059,200
11,059,200
32,000
32,000
32,000
=
††
††
††
(
256 PCA0CPL2
×
Rev. 2.3
PCA0CPL2
)
255
128
255
128
255
128
255
128
255
128
+
32
32
32
32
32
(
256 PCA0L
C8051F300/1/2/3/4/5
–
Timeout Interval (ms)
)
†
24576
12384
129.5
3168
32.1
16.2
42.7
21.5
71.1
35.8
33.1
257
4.1
5.5
9.2
157