C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 127

IC 8051 MCU 8K FLASH 11MLP

C8051F302

Manufacturer Part Number
C8051F302
Description
IC 8051 MCU 8K FLASH 11MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Datasheets

Specifications of C8051F302

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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14.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave pro-
cessors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first
sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in
a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is received, the
UART will generate an interrupt only if the ninth bit is logic one (RB80 = 1) signifying an address byte has been
received. In the UART interrupt handler, software will compare the received address with the slave's own assigned 8-
bit address. If the addresses match, the slave will clear its MCE0 bit to enable interrupts on the reception of the fol-
lowing data byte(s). Slaves that weren't addressed leave their MCE0 bits set and do not generate interrupts on the
reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed
slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be con-
figured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily
reversed to enable half-duplex transmission between the original master and slave(s).
RX
Master
Device
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram
TX
RX
Device
Slave
TX
RX
Device
Slave
Rev. 2.3
TX
C8051F300/1/2/3/4/5
RX
Device
Slave
TX
+5V
127

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