C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 146

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

C8051F300/1/2/3/4/5
16.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the
16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H
into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Regis-
ter first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not
disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD register select the timebase for the counter/timer
as shown in Table 16.1. Note that in ‘External oscillator source divided by 8’ mode, the external oscillator
source is synchronized with the system clock, and must have a frequency less than or equal to the system clock.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be glo-
bally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit and the
EPCA0 bit to logic 1). Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation
while the CPU is in Idle mode.
146
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
†
External oscillator source divided by 8 is synchronized with the system clock.
CPS2
0
0
0
0
1
1
C
D
L
I
W
D
T
E
PCA0MD
W
D
L
C
K
CPS1
0
0
1
1
0
0
C
P
S
2
000
001
010
011
100
101
C
P
S
1
C
P
S
0
Figure 16.2. PCA Counter/Timer Block Diagram
E
C
F
CPS0
Table 16.1. PCA Timebase Input Options
IDLE
0
1
0
1
0
1
C
F
C
R
PCA0CN
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
System clock
External oscillator source divided by 8
C
C
F
2
C
C
F
1
C
C
F
0
Rev. 2.3
0
1
PCA0L
read
Snapshot
Register
PCA0H
PCA0L
†
To SFR Bus
To PCA Modules
Overflow
CF
To PCA Interrupt System