C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 119

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR
refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response
options are only the typical responses; application-specific procedures are allowed as long as they conform with the
SMBus specification. Highlighted responses are allowed but do not conform to the SMBus specification.
1000
1110
1100
VALUES READ
0
0
0
1
0
0
0
0
X A master START was generated.
X
0
1
A master data or address byte was
transmitted; NACK received.
A master data or address byte was
transmitted; ACK received.
A master data byte was received;
ACK requested.
CURRENT SMBUS STATE
Table 13.4. SMBus Status Decoding
Rev. 2.3
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT
End transfer with STOP
End transfer with STOP and
start another transfer.
Send repeated START
Switch to Master Receiver
Mode (clear SI without writing
new data to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last
byte, and send STOP.
Send NACK to indicate last
byte, and send STOP followed
by START.
Send ACK followed by
repeated START.
Send NACK to indicate last
byte, and send repeated START.
Send ACK and switch to Mas-
ter Transmitter Mode (write
to SMB0DAT before clearing
SI).
Send NACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
TYPICAL RESPONSE
C8051F300/1/2/3/4/5
OPTIONS
WRITTEN
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
VALUES
0
0
1
0
1
1
0
0
0
1
1
0
0
0
0
119
X
X
X
X
X
X
X
X
1
0
0
1
0
1
0