HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 13

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section
8.3.3 Precautions
when Using the Sleep
Mode
8.5.1 Transition to
Module Standby
Function
9.3 Clock Operating
Modes
Table 9.4 Available
Combinations of Clock
Mode and FRQCR
Values
9.5.1 Changing the
Multiplication Rate
9.8.2 Changing the
Frequency
10.1.1 Features
10.2.5 Individual
Memory Control
Register (MCR)
Page
187
191
210
213
218,
219
223
246
Note: 3. Before putting the RTC into module standby status, first
The peripheral clock frequency should not be set higher than the
Description
Newley added
Note *3 added to bit table
2. under cautions amended
frequency of the CKIO pin, higher than 33.34 MHz.
Description added
5.Supply of the clock that has been set begins at WDT count
When the following three conditions are all met, FRQCR should
not be changed while a DMAC transfer is in progress.
• Bits IFC2 to IFC0 are changed.
• STC2 to STC0 are not changed.
• The clock ratio of I (on-chip clock) to B (bus clock) after the
change is other than 1:1.
Description added
5.The counter stops at a value of H'00 or H'01. The stop value
depends on the clock ratio.
When the following three conditions are all met, FRQCR should
not be changed while a DMAC transfer is in progress.
• Bits IFC2 to IFC0 are changed.
• STC2 to STC0 are not changed.
• The clock ratio of I (on-chip clock) to B (bus clock) after the
change is other than 1:1.
Refresh function description deleted
Description added
Bit 7—Synchronous DRAM Bank Active (RASD): Specifies
whether synchronous DRAM is used in bank active mode or auto-
precharge mode. Set auto-precharge mode when areas 2 and 3
are both designated as synchronous DRAM space.
The bank active mode should not be used unless the bus width
for all areas is 32 bits.
overflow, and the processor begins operating again. The WDT
stops after it overflows.
access one or more of the RTC, SCI, and TMU
registers. The RTC may then be put into module standby
status.
Rev. 5.0, 09/03, page xi of xliv