HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 189

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4
6.4.1
The sequence of interrupt operations is described below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
3. The priority level of the interrupt selected by the interrupt controller is compared with the
4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in
5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
Notes: 1. The interrupt mask bits (I3–I0) in the status register (SR) are not changed by
following the priority levels set in interrupt priority registers A to E (IPRA to IPRE). Lower
priority interrupts are held pending. If two of these interrupts have the same priority level or if
multiple interrupts occur within a single module, the interrupt with the highest default priority
or the highest priority within its IPR setting unit (as indicated in tables 6.4 and 6.5) is selected.
interrupt mask bits (I3–I0) in the status register (SR) of the CPU. If the request priority level is
higher than the level in bits I3–I0, the interrupt controller accepts the interrupt and sends an
interrupt request signal to the CPU. When the interrupt controller receives an interrupt, a low
level is output from the IRQOUT pin.
synchronization with the peripheral clock (P ). The CPU receives an interrupt at a break in
instructions.
vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt
handler may branch with the INTEVT and INTEVT2 register value as its offset in order to
identify the interrupt source. This enables it to branch to the handling routine for the individual
interrupt source.
2. IRQOUT outputs a low level until the interrupt request is cleared. However, if the
3. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
INTC Operation
Interrupt Sequence
acceptance of an interrupt in the SH7709S.
interrupt source is masked by an interrupt mask bit, the IRQOUT pin returns to the
high level. The level is output without regard to the BL bit.
interrupt request that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, then wait for the interval shown in
table 6.8 (Time for priority decision and SR mask bit comparison) before clearing the
BL bit or executing an RTE instruction.
Rev. 5.00, 09/03, page 143 of 760