HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 565

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data.
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the
Bit 4—Parity Mode (O/E E E E ): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition
and checking. The O/E setting is ignored when parity addition and checking is disabled.
Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length.
When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character.
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 5: PE
0
1
Bit 4: O/E E E E
0
1
Bit 3: STOP
0
1
2. If odd parity is selected, the parity bit is added to transmit data to make an odd number
2. When transmitting, two 1-bits are added at the end of each transmitted character.
parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
number of 1s in the transmitted character and parity bit combined. Receive data is
checked to see if it has an even number of 1s in the received character and parity bit
combined.
of 1s in the transmitted character and parity bit combined. Receive data is checked to
see if it has an odd number of 1s in the received character and parity bit combined.
Description
Parity bit not added or checked
Parity bit added and checked *
Description
Even parity *
Odd parity *
Description
One stop bit *
Two stop bits *
2
1
1
2
Rev. 5.00, 09/03, page 519 of 760
(Initial value)
(Initial value)
(Initial value)