HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 40

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 23.47 TCLK Input Timing ............................................................................................. 707
Figure 23.48 TCLK Clock Input Timing................................................................................... 707
Figure 23.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on............................ 707
Figure 23.50 SCK Input Clock Timing ..................................................................................... 707
Figure 23.51 SCI I/O Timing in Clock Synchronous Mode ...................................................... 708
Figure 23.52 I/O Port Timing .................................................................................................... 708
Figure 23.53 DREQ Input Timing............................................................................................. 708
Figure 23.54 DRAK Output Timing.......................................................................................... 709
Figure 23.55 TCK Input Timing................................................................................................ 709
Figure 23.56 TRST Input Timing (Reset Hold)......................................................................... 710
Figure 23.57 UDI Data Transfer Timing ................................................................................... 710
Figure 23.58 ASEMD0 Input Timing........................................................................................ 710
Figure 23.59 Output Load Circuit.............................................................................................. 711
Figure 23.60 Load Capacitance vs. Delay Time........................................................................ 712
Figure D.1
Figure D.2
Figure D.3
Rev. 5.00, 09/03, page xxxviii of xliv
Package Dimensions (FP-208C)........................................................................... 758
Package Dimensions (FP-208E)........................................................................... 759
Package Dimensions (BP-240A).......................................................................... 760