HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 151

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

The LRU bits are initialized to 000000 by a power-on reset, but are not initialized by a manual
reset.
Table 5.2
LRU (5–0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
5.1.3
Table 5.3 shows details of the cache control register.
Table 5.3
Register
Cache control register
Cache control register 2
Note: * When address translation by the MMU does not apply, the address in parentheses should
5.2
5.2.1
The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also
has a CF bit (which invalidates all cache entries), and a WT and CB bits (which select either write-
through mode or write-back mode). Programs that change the contents of the CCR register should
be placed in address space that is not cached. When updating the contents of the CCR register,
always set bits 4 to 0. Figure 5.2 shows the configuration of the CCR register.
be used.
Register Configuration
Register Description
Cache Control Register (CCR)
LRU and Way Replacement (When the cache lock function is not used)
Register Configuration
Abbr.
CCR
CCR2
R/W
R/W
R/W
Initial Value
H'00000000
H'00000000
Way to be Replaced
3
2
1
0
Rev. 5.00, 09/03, page 105 of 760
Address
H'FFFFFFEC
H'040000B0
(H’A40000B0) *
32-bit
32-bit
Access Size