HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 481

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In the
synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit data register (SCTDR) is not
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added
nor checked, regardless of the PE setting.
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the
Bit 4—Parity Mode (O/E E E E ): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set
to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, or in
asynchronous mode when parity addition and checking is disabled.
Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even
Bit 6: CHR
0
1
Bit 5: PE
0
1
Bit 4: O/E E E E
0
1
2. If odd parity is selected, the parity bit is added to transmit data to make an odd number
transmitted.
parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
number of 1s in the transmitted character and parity bit combined. Receive data is
checked to see if it has an even number of 1s in the received character and parity bit
combined.
of 1s in the transmitted character and parity bit combined. Receive data is checked to
see if it has an odd number of 1s in the received character and parity bit combined.
Description
8-bit data
7-bit data *
Description
Parity bit not added or checked
Parity bit added and checked *
Description
Even parity *
Odd parity *
2
1
Rev. 5.00, 09/03, page 435 of 760
(Initial value)
(Initial value)
(Initial value)