HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 540

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 3 to 0: These bits have the same function as in the ordinary SCI. See section 14, Serial
Communication Interface (SCI), for more information. The setting conditions for bit 2, the
transmit end bit (TEND), are changed as follows.
Bit 2: TEND
0
1
Note: etu: Elementary Time Unit (time for transfer of 1 bit).
15.3
15.3.1
The primary functions of the smart card interface are described below.
1. Each frame consists of 8-bit data and 1 parity bit.
2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: time
3. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed
4. During transmission, it automatically transmits the same data after allowing at least 2 etu from
5. Only start-stop type asynchronous communication functions are supported; no synchronous
Rev. 5.00, 09/03, page 494 of 760
for transfer of 1 bit) from the end of the parity bit to the start of the next frame.
from the start bit if a parity error was detected.
the time the error signal is sampled.
communication functions are available.
Operation
Overview
Description
Transmission is in progress
[Clearing condition]
Cleared by reading TDRE when TDRE = 1, then writing 0 to TDRE
End of transmission
[Setting conditions]
(1) the chip is reset or enters standby mode,
(2) the TE bit in SCSCR is 0 and the FER/ERS bit is also 0,
(3) the C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal
(4) the C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 2.5 etu after a one-byte serial character is transmitted, or
transmission) 1.0 etu after a one-byte serial character is transmitted.
(Initial value)