HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 533

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

The receive margin in asynchronous mode can therefore be expressed as in equation 1.
Equation 1:
Where:
From equation 1, if F
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Notes on Synchronous External Clock Mode:
Note on Synchronous Internal Clock Mode: When receiving, RDRF is set to 1 when RE is cleared
to zero 1.5 clocks after the rising edge of the SCK output of the D7 bit in RxD, but data cannot be
copied to SCRDR.
Do not set TE
to 1.
Set TE
When receiving, RDRF is set to 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of
the SCK input of the D7 bit in RxD, but data cannot be copied to SCRDR.
M = 0.5
M
M
N
D
L Frame length (L
F
RE 1 only when external clock SCK is 1.
Absolute deviation of clock frequency
(0.5 – 1/(2
46.875
Ratio of clock frequency to bit rate (N
Clock duty cycle (D
Receive margin ( )
RE
2N
1
0 and D
1 until at least four clocks after external clock SCK has changed from 0
16))
(L
0.5)F
9 to 12)
100
0.5, the receive margin is 46.875%, as in equation 2.
0 to 1.0)
D
N
0.5
(1 + F)
16)
100%
Rev. 5.00, 09/03, page 487 of 760