HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 667

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

20.2.3
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'07 by a reset and in standby mode.
Bit 7 and 6—Trigger Enable (TRGE1, TRGE0): Enables or disables external triggering of A/D
conversion.
The TRGE1 and TRGE0 bits should only be set when conversion is not in progress.
Bit 5—Scan Mode (SCN): Selects multi mode or scan mode when the MULTI bit is set to 1. See
the description of bit 4 in section 20.2.2, A/D Control/Status Register (ADCSR).
Bits 4 and 3—Reserved (RESVD1, RESVD2): These bits are always read as 0. The write value
should always be 0.
Bits 2 to 0—Reserved: These bits are always read as 1. The write value should always be 1.
Bit 7: TRGE1
0
0
1
1
Initial value:
R/W:
A/D Control Register (ADCR)
Bit:
TRGE1
R/W
Bit 6: TRGE0
0
1
0
1
7
0
TRGE0
R/W
6
0
Description
A/D conversion does not start when an external trigger is input
A/D conversion starts at the falling edge of an input signal from
the external trigger pin (ADTRG)
SCN
R/W
5
0
RESVD1 RESVD2
R/W
4
0
R/W
3
0
Rev. 5.00, 09/03, page 621 of 760
—
R
2
1
—
R
1
1
(Initial value)
—
R
0
1