HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 41

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Tables
Table 1.1
Table 1.2
Table 1.3
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 3.1
Table 3.2
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8
Table 7.1
Table 7.2
Table 8.1
SH7709S Features ..................................................................................................
Characteristics.........................................................................................................
SH7709S Pin Function ...........................................................................................
Initial Register Values ............................................................................................ 22
Addressing Modes and Effective Addresses........................................................... 28
Instruction Formats ................................................................................................. 32
Classification of Instructions .................................................................................. 35
Instruction Code Format ......................................................................................... 38
Data Transfer Instructions ...................................................................................... 39
Arithmetic Instructions ........................................................................................... 41
Logic Operation Instructions .................................................................................. 44
Shift Instructions..................................................................................................... 45
Branch Instructions ................................................................................................. 46
System Control Instructions.................................................................................... 47
Instruction Code Map ............................................................................................. 50
Register Configuration............................................................................................ 61
Access States Designated by D, C, and PR Bits ..................................................... 68
Register Configuration............................................................................................ 85
Exception Event Vectors ........................................................................................ 87
Exception Codes ..................................................................................................... 90
Types of Reset ........................................................................................................ 95
Cache Specifications............................................................................................... 103
LRU and Way Replacement (When the cache lock function is not used) .............. 105
Register Configuration............................................................................................ 105
Way Replacement when PREF Instruction Ended Up in a Cache Miss ................. 107
Way Replacement when Instructions Except for PREF Instruction Ended Up
in a Cache Miss....................................................................................................... 108
LRU and Way Replacement (when W2LOCK=1) ................................................. 108
LRU and Way Replacement (when W3LOCK=1) ................................................. 108
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)..................... 108
INTC Pins ............................................................................................................... 119
INTC Registers ....................................................................................................... 120
IRL3–IRL0/IRLS3–IRLS0 Pins and Interrupt Levels ............................................ 123
Interrupt Exception Handling Sources and Priority (IRQ Mode) ........................... 126
Interrupt Exception Handling Sources and Priority (IRL Mode)............................ 128
Interrupt Levels and INTEVT Codes...................................................................... 130
Interrupt Request Sources and IPRA–IPRE............................................................ 131
Interrupt Response Time......................................................................................... 146
Register Configuration............................................................................................ 151
Data Access Cycle Addresses and Operand Size Comparison Conditions............. 171
Power-Down Modes ............................................................................................... 182
Rev. 5.00, 09/03, page xxxix of xliv
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