HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 23

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.5
8.6
8.7
Section 9 On-Chip Oscillation Circuits
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
8.4.1
8.4.2
8.4.3
Module Standby Function ................................................................................................. 191
8.5.1
8.5.2
Timing of STATUS Pin Changes ...................................................................................... 192
8.6.1
8.6.2
8.6.3
Hardware Standby Mode................................................................................................... 199
8.7.1
8.7.2
8.7.3
Overview ........................................................................................................................... 203
9.1.1
Overview of CPG .............................................................................................................. 204
9.2.1
9.2.2
9.2.3
Clock Operating Modes..................................................................................................... 207
Register Descriptions......................................................................................................... 211
9.4.1
Changing the Frequency.................................................................................................... 213
9.5.1
9.5.2
Overview of WDT............................................................................................................. 214
9.6.1
9.6.2
WDT Registers .................................................................................................................. 215
9.7.1
9.7.2
9.7.3
Using the WDT ................................................................................................................. 218
9.8.1
9.8.2
9.8.3
9.8.4
Notes on Board Design...................................................................................................... 220
Clock Pause Function........................................................................................... 190
Transition to Module Standby Function............................................................... 191
Timing for Canceling Standby ............................................................................. 194
Features ................................................................................................................ 203
Changing the Multiplication Rate ........................................................................ 213
Changing the Division Ratio ................................................................................ 213
Transition to Standby Mode ................................................................................. 188
Canceling Standby Mode ..................................................................................... 189
Clearing Module Standby Function...................................................................... 191
Timing for Resets ................................................................................................. 192
Timing for Canceling Sleep Mode ....................................................................... 196
Transition to Hardware Standby Mode ................................................................ 199
Canceling Hardware Standby Mode..................................................................... 199
Hardware Standby Mode Timing ......................................................................... 200
CPG Block Diagram............................................................................................. 204
CPG Pin Configuration ........................................................................................ 206
CPG Register Configuration................................................................................. 206
Frequency Control Register (FRQCR) ................................................................. 211
Block Diagram of WDT ....................................................................................... 214
Register Configuration ......................................................................................... 214
Watchdog Timer Counter (WTCNT) ................................................................... 215
Watchdog Timer Control/Status Register (WTCSR) ........................................... 215
Notes on Register Access ..................................................................................... 217
Canceling Standby................................................................................................ 218
Changing the Frequency....................................................................................... 218
Using Watchdog Timer Mode .............................................................................. 219
Using Interval Timer Mode .................................................................................. 219
......................................................................... 203
Rev. 5.00, 09/03, page xxi of xliv