HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 443

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

12.2.4
The TMU has three TCOR registers, one for each channel. TCOR specifies the value for setting in
TCNT when a TCNT count-down results in an under flow.
TCOR is a 32-bit readable/writable register. TCOR is initialized to H'FFFFFFFF by a power-on
reset or manual reset, but is not initialized, and retains its contents, in standby mode.
12.2.5
The timer counters are 32-bit readable/writable registers. The TMU has three timer counters, one
for each channel.
TCNT counts down upon input of a clock. The clock input is selected using the TPSC2–TPSC0
bits in the timer control register (TCR).
When a TCNT count-down results in an underflow (H'00000000
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the count-down continues from that value.
Initial value:
Initial value:
Initial value:
Initial value:
Timer Constant Registers (TCOR)
Timer Counters (TCNT)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/W
R/W
R/W
R/W
31
23
15
1
1
1
7
1
R/W
R/W
R/W
R/W
30
22
14
1
1
1
6
1
R/W
R/W
R/W
R/W
29
21
13
1
1
1
5
1
R/W
R/W
R/W
R/W
28
20
12
1
1
1
4
1
R/W
R/W
R/W
R/W
27
19
11
1
1
1
3
1
Rev. 5.00, 09/03, page 397 of 760
H'FFFFFFFF), the underflow
R/W
R/W
R/W
R/W
26
18
10
1
1
1
2
1
R/W
R/W
R/W
R/W
25
17
1
1
9
1
1
1
R/W
R/W
R/W
R/W
24
16
1
1
8
1
0
1