HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 157

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5.3.2
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
transfer unit is 32 bits. The LRU is updated.
Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one
least recently used. Entries are updated in 16-byte units. When the desired instruction or data that
caused the miss is loaded from external memory to the cache, the instruction or data is transferred
to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is
cleared to 0 and the V bit is set to 1.
5.3.3
Prefetch Hit: The LRU will be updated to correctly indicate the latest way to have been hit. Other
contents of the cache will remain unchanged. Neither instructions nor data are transferred to the
CPU.
Prefetch Miss: Neither instructions nor data are transferred to the CPU, and way replacement
takes place as shown in table 5.4. All other action is the same as for a read miss.
5.3.4
Write Hit: In a write access in the write-back mode, the data is written to the cache and the U bit
of the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is
issued. In the write-through mode, the data is written to the cache and an external memory write
cycle is issued.
Write Miss: In the write-back mode, an external write cycle starts when a write miss occurs, and
the entry is updated. The way to be replaced is shown in table 5.5. When the U bit of the entry to
be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer.
The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1. After the
cache completes its fill cycle, the write-back buffer writes back the entry to the memory. In the
write-through mode, no write to cache occurs in a write miss; the write is only to the external
memory.
5.3.5
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to
the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. During the write back cycles, the cache can be accessed. The write-back buffer
can hold one line of the cache data (16 bytes) and its physical address. Figure 5.5 shows the
configuration of the write-back buffer.
Read Access
Prefetch Operation
Write Access
Write-Back Buffer
Rev. 5.00, 09/03, page 111 of 760