HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 514

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI transfers data
Figure 14.14 shows SCI transmission with a multiprocessor format.
Rev. 5.00, 09/03, page 468 of 760
TXI interrupt
request
generated
that the transmit data register (SCTDR) contains new data, and transfers this data from SCTDR
into the transmit shift register (SCTSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCSCR is set to 1, the SCI
requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted
in the following order from the TxD pin:
a. Start bit: One 0-bit is output.
b. Transmit data: Seven or eight bits are output, LSB first.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit: One or two 1-bits (stop bits) are output.
e. Marking: Output of 1-bits continues until the start bit of the next transmit data.
from SCTDR into SCTSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit in SCSSR to 1, outputs the stop bit, then
continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in
SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
TDRE
TEND
Serial
data
1
Figure 14.14 Example of SCI Multiprocessor Transmit Operation
Start
bit
0
Writes data to TDR
with the TXI interrupt
processing routine
and clears TDRE
bit to 0
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
D
0
D
1 frame
1
Data
D
processor
7
Multi-
bit
0/1
TXI interrupt
request
generated
Stop
bit
1
Start
bit
0
D
0
D
1
Data
D
processor
7
Multi-
bit
0/1
TEI interrupt
request
generated
Stop
bit
1
Idle (mark)
state
1