HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 569

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 7—Receive Error (ER): Indicates the occurrence of a framing error, or of a parity error when
receiving data that includes parity.
Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous
Bit 6—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, SCFTDR did not contain valid data, so transmission has ended.
Bit 7: ER
0
1
Bit 6: TEND
0
1
2. In stop mode, only the first stop bit is checked; the second stop bit is not checked.
value. Even if a receive error occurs, the receive data is transferred to SCFRDR and
the receive operation is continued. Whether or not the data read from SCRDR includes
a receive error can be detected by the FER and PER bits in SCSSR.
Description
Receiving is in progress or has ended normally *
[Clearing conditions]
(1) By a power-on reset or in standby mode ER is cleared to 0 when the chip is
(2) When 0 is written after 1 is read from ER
A framing error or parity error has occurred *
[Setting conditions]
(1) ER is set to 1 when the stop bit is 0 after checking whether or not the last
(2) When the total number of 1s in the receive data plus parity bit does not match
Description
Transmission is in progress
[Clearing condition]
When data is written in SCFTDR
End of transmission
[Setting conditions]
(1) When the chip is reset or enters standby mode, when TE is cleared to 0 in
(2) When SCFTDR does not contain receive data when the last bit of a one-byte
reset or enters standby mode
stop bit of the received data is 1 at the end of one data receive operation *
the even/odd parity specified by the O/E bit in SCSMR
the serial control register (SCSCR)
serial character is transmitted
2
Rev. 5.00, 09/03, page 523 of 760
1
(Initial value)
(Initial value)
2