HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 144

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 5.00, 09/03, page 98 of 760
Illegal slot instruction
User break point trap
DMA address error
Conditions:
a. When undefined code in a delay slot is decoded
b. When an instruction that rewrites PC in a delay slot is decoded
c. When a privileged instruction in a delay slot is decoded in user mode
Operations: PC of the immediately preceding delay branch instruction is saved to SPC. SR
of the instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT.
The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
When an undefined instruction other than H'Fxxx is decoded, operation cannot be
guaranteed.
Conditions: When a break condition set in the user break controller is satisfied
Operations: When a post-execution break occurs, PC of the instruction immediately after
the instruction that set the break point is set in SPC. If a pre-execution break occurs, PC of
the instruction that set the break point is set in SPC. SR when the break occurs is set in
SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch
occurs to PC
Conditions:
a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
Operations: PC of the instruction immediately after the instruction executed before the
exception occurs is saved to SPC. SR when the exception occurs is saved to SSR. H'5C0 is
set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC
VBR + H'0100.
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; Instructions that access
GBR with LDC/STC are not privileged instructions and therefore do not apply.
4n + 3)
VBR + H'0100. See section 7, User Break Controller, for more information.