HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 265

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

When the following three conditions are all met, FRQCR should not be changed while a DMAC
transfer is in progress.
9.8.3
1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
9.8.4
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2–
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval
count clock in the CKS2–CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
the counter from overflowing.
type of reset specified by the RSTS bit. The counter then resumes counting. When a reset is
generated, a low level is output at the RESETOUT pin, and a high level at the STATUS0 and
STATUS1 pins. The output period is approximately 1 count clock cycle in the case of a power-
on reset, and approximately 5 peripheral clock cycles in the case of a manual reset.
CKS0 bits, and set the initial value of the counter in the WTCNT counter.
timer interrupt request is sent to the INTC. The counter then resumes counting.
Bits IFC2 to IFC0 are changed.
STC2 to STC0 are not changed.
The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1.
Using Watchdog Timer Mode
Using Interval Timer Mode
Rev. 5.00, 09/03, page 219 of 760