HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 668

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

20.3
ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8
bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly
by the bus master, the lower byte is read through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the bus master.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed.
Figure 20.2 shows the data flow for access to an A/D data register.
See section 20.7.3, Access Size and Read Data.
Rev. 5.00, 09/03, page 622 of 760
Upper byte read
Lower byte read
Bus Master Interface
(H'AA)
(H'40)
CPU
CPU
Figure 20.2 A/D Data Register Access Operation (Reading H'AA40)
interface
interface
Bus
Bus
ADDRn H
ADDRn H
[H'AA]
[H'AA]
Module internal data bus
Module internal data bus
ADDRn L
ADDRn L
TEMP
TEMP
[H'40]
[H'40]
[H'40]
[H'40]
n = A to D