HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 567

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and
receive-error (ERI) interrupts requested when serial receive data is transferred from the receive
shift register (SCRSR) to the receive FIFO data register (SCFRDR), when the quantity of data in
the receive FIFO register becomes more than the specified receive trigger number, and when the
RDRF flag in SCSSR is set to1.
Note: * RXI and ERI interrupt requests can be cleared by reading the DR, ER, or RDF flag after it
Bit 5—Transmit Enable (TE): Enables or disables the SCIF serial transmitter.
Note: * Serial transmission starts after writing of transmit data into SCFTDR2. Select the transmit
Bit 4—Receive Enable (RE): Enables or disables the SCIF serial receiver.
Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, FER, PER, and
Bits 3 and 2—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 6: RIE
0
1
Bit 5: TE
0
1
Bit 4: RE
0
1
2. Serial reception starts when a start bit is detected. Select the receive format in
has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. With the RDF flag,
read 1 from the RDF flag and clear it to 0, after reading receive data from SCRDR until the
quantity of receive data becomes less than the specified receive trigger number.
format in SCSMR2 and SCFCR2 and reset the TFIFO before setting TE to 1.
ORER). These flags retain their previous values.
SCSMR2 before setting RE to 1.
Description
Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and receive break
interrupt (BRI) requests are disabled *
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
enabled
Description
Transmitter disabled
Transmitter enabled *
Description
Receiver disabled *
Receiver enabled *
2
1
Rev. 5.00, 09/03, page 521 of 760
(Initial value)
(Initial value)
(Initial value)