HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 399

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(1) In direct address transfer mode, DMA transfer requires two bus cycles because data is read
from the transfer source in a data read cycle and written to the transfer destination in a
data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the
transfer between external memories as shown in figure 11.5, data is read to the DMAC
from one external memory in a data read cycle, and then that data is written to the other
external memory in a write cycle. Figure 11.6 shows an example of the timing at this
time.
Figure 11.5 Operation of Direct Address Mode in Dual Address Mode
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
The DAR value is an address, and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Data buffer
Data buffer
DMAC
DMAC
SAR
DAR
SAR
DAR
Second bus cycle
First bus cycle
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module
Rev. 5.00, 09/03, page 353 of 760