HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 245

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.7
8.7.1
Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode,
all modules except those operating on an RTC clock are halted, as in the standby mode entered on
execution of a SLEEP instruction ((software) standby mode).
Hardware standby mode differs from (software) standby mode as follows.
1. Interrupts and manual resets are not accepted.
2. The TMU does not operate.
Operation when a low-level signal is input at the CA pin depends on the CPG state, as follows.
1. In standby mode
2. During WDT operation when standby mode is canceled by an interrupt
3. In sleep mode
Hold the CA pin low in hardware standby mode.
8.7.2
Hardware standby mode can only be canceled by a power-on reset.
When the CA pin is driven high while the RESETP pin is low, clock oscillation is started. Hold
the RESETP pin low until clock oscillation stabilizes. When the RESETP pin is driven high, the
CPU begins power-on reset processing.
Operation is not guaranteed in the event of an interrupt or manual reset.
The clock remains stopped and the chip enters the hardware standby state. Acceptance of
interrupts and manual resets is disabled, TCLK output is fixed low, and the TMU halts.
The chip enters hardware standby mode after standby mode is canceled and the CPU resumes
operation.
The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes
operation.
Hardware Standby Mode
Transition to Hardware Standby Mode
Canceling Hardware Standby Mode
Rev. 5.00, 09/03, page 199 of 760