HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 38

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 19.8
Figure 19.9
Figure 19.10 Port K ................................................................................................................... 605
Figure 19.11 Port L.................................................................................................................... 607
Figure 19.12 SC Port ................................................................................................................. 609
Figure 20.1
Figure 20.2
Figure 20.3
Figure 20.4
Figure 20.5
Figure 20.6
Figure 20.7
Figure 20.8
Figure 20.9
Figure 20.10 Analog Input Pin Equivalent Circuit .................................................................... 633
Figure 21.1
Figure 21.2
Figure 22.1
Figure 22.2
Figure 22.3
Figure 23.1
Figure 23.2
Figure 23.3
Figure 23.4
Figure 23.5
Figure 23.6
Figure 23.7
Figure 23.8
Figure 23.9
Figure 23.10 PLL Synchronization Settling Time when Frequency Multiplication Rate
Figure 23.11 Reset Input Timing............................................................................................... 671
Figure 23.12 Interrupt Signal Input Timing............................................................................... 671
Figure 23.13 IRQOUT Timing .................................................................................................. 671
Figure 23.14 Bus Release Timing.............................................................................................. 672
Figure 23.15 Pin Drive Timing at Standby................................................................................ 672
Figure 23.16 Basic Bus Cycle (No Wait) .................................................................................. 675
Figure 23.17 Basic Bus Cycle (One Wait)................................................................................. 676
Figure 23.18 Basic Bus Cycle (External Wait, WAITSEL = 1) ................................................ 677
Rev. 5.00, 09/03, page xxxvi of xliv
Port H ................................................................................................................... 601
Port J .................................................................................................................... 603
Block Diagram of A/D Converter ........................................................................ 614
A/D Data Register Access Operation (Reading H'AA40) .................................... 622
Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ......... 624
Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2
Selected) ............................................................................................................... 626
Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Selected) ............................................................................................................... 628
A/D Conversion Timing ....................................................................................... 629
External Trigger Input Timing ............................................................................. 630
Definitions of A/D Conversion Accuracy ............................................................ 632
Example of Analog Input Protection Circuit ........................................................ 633
Block Diagram of D/A Converter ........................................................................ 635
Example of D/A Converter Operation.................................................................. 639
Block Diagram of UDI ......................................................................................... 642
TAP Controller State Transitions ......................................................................... 651
UDI Reset............................................................................................................. 653
EXTAL Clock Input Timing ................................................................................ 665
CKIO Clock Input Timing ................................................................................... 665
CKIO Clock Output Timing................................................................................. 665
Power-on Oscillation Settling Time ..................................................................... 666
Oscillation Settling Time at Standby Return (Return by Reset)........................... 666
Oscillation Settling Time at Standby Return (Return by NMI)............................ 667
Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0,
PINT0/1, IRL3 to IRL0)....................................................................................... 667
PLL Synchronization Settling Time during Standby Recovery (Reset or NMI) .. 668
PLL Synchronization Settling Time during Standby Recovery (IRQ/IRL or
PINT0/PINT1 Interrupt)....................................................................................... 668
Modified ............................................................................................................... 669