HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 216

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7.3
7.3.1
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses and the corresponding ASIDs are loaded in the break address registers
2. When the break conditions are satisfied, the UBC sends a user break request to the interrupt
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
4. There is a chance that the data access break and its following instruction fetch break occur
7.3.2
1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers
2. An instruction set for a break before execution breaks when it is confirmed that the instruction
Rev. 5.00, 09/03, page 170 of 760
(BARA and BARB) and break ASID registers (BASRA and BASRB). The masked addresses
are set in the break address mask registers (BAMRA and BAMRB). The break data is set in the
break data register (BDRB). The masked data is set in the break data mask register (BDMRB).
The breaking bus conditions are set in the break bus cycle registers (BBRA and BBRB). Three
groups of the BBRA and BBRB (CPU cycle/DMAC cycle select, instruction fetch/data access
select, and read/write select) are each set. No user break will be generated if even one of these
groups is set with 00. The respective conditions are set in the bits of the BRCR.
controller. The break type will be sent to CPU indicating the instruction fetch, pre/post
instruction break, data access break. When conditions match up, the CPU condition match
flags (SCMFCA and SCMFCB) and DMAC condition match flags (SCMFDA and SCMFDB)
for the respective channels are set.
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. 0 must first be written to them before they can be used again.
around the same time, there will be only one break request to the CPU, but these two break
channel match flags could be both set.
(BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then
breaks before or after the execution of the instruction can then be selected with the
PCBA/PCBB bits of the break control register (BRCR) for the appropriate channel.
has been fetched and will be executed. This means this feature cannot be used on instructions
fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to
be executed). When this kind of break is set for the delay slot of a delay branch instruction, the
break is generated prior to execution of the instruction that then first accepts the break.
Meanwhile, the break set for pre-instruction-break on delay slot instruction and post-
instruction-break on SLEEP instruction are also prohibited.
Operation Description
Flow of the User Break Operation
Break on Instruction Fetch Cycle