HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 511

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 14.11 shows an example of SCI receive operation in asynchronous mode.
14.3.3
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which
it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting
processor sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 14.12 shows an example of communication among processors using the multiprocessor
format.
RDRF
Serial
FER
data
Multiprocessor Communication
1
Start
bit
0
D
0
Figure 14.11 Example of SCI Receive Operation
D
(8-Bit Data with Parity and One Stop Bit)
1
1 frame
Data
D
7
RXI interrupt
request generated
Parity
bit
0/1
Stop
bit
1
RXI interrupt handler
reads data and clears
RDRF bit to 0
Start
bit
0
D
0
D
1
Data
Rev. 5.00, 09/03, page 465 of 760
D
7
Parity
bit
0/1
ERI interrupt
request generated
by framing error
Stop
bit
1
Idle (mark)
state
1