HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 507

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 14.9 shows an example of SCI transmit operation in asynchronous mode.
Receiving Serial Data (Asynchronous Mode): Figure 14.10 shows a sample flowchart for
receiving serial data. The procedure for receiving serial data after enabling the SCI for reception
is:
1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER and
2. SCI status check and receive-data read: Read the serial status register (SCSSR), check that
3. To continue receiving serial data: Read the RDRF and SCRDR bits and clear RDRF to 0
TXI interrupt
request
generated
TDRE
TEND
Serial
FER bits in SCSSR to identify the error. After executing the necessary error handling, clear
ORER, PER and FER to 0. Receiving cannot resume if ORER, PER or FER remains set to 1.
When a framing error occurs, the RxD pin can be read to detect the break state.
RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear
RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from
0 to 1.
before the stop bit of the current frame is received.
data
1
Figure 14.9 Example of SCI Transmit Operation in Asynchronous Mode
Start
bit
0
TXI interrupt
handler writes
data to SCTDR
and clears
TDRE bit to 0
D
0
(8-Bit Data with Parity and One Stop Bit)
D
1 frame
1
Data
D
TXI interrupt
request
generated
7
Parity
bit
0/1
Stop
bit
1
Start
bit
0
D
0
D
1
Rev. 5.00, 09/03, page 461 of 760
Data
D
7
Parity
bit
0/1
TEI interrupt
request
generated
Stop
bit
1
Idle (mark)
state
1