HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 22

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 User Break Controller
7.1
7.2
7.3
Section 8 Power-Down Modes
8.1
8.2
8.3
8.4
Rev. 5.00, 09/03, page xx of xliv
Overview ........................................................................................................................... 149
7.1.1
7.1.2
7.1.3
Register Descriptions......................................................................................................... 152
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10 Execution Times Break Register (BETR) ............................................................ 166
7.2.11 Branch Source Register (BRSR) .......................................................................... 167
7.2.12 Branch Destination Register (BRDR) .................................................................. 168
7.2.13 Break ASID Register A (BASRA) ....................................................................... 169
7.2.14 Break ASID Register B (BASRB) ....................................................................... 169
Operation Description ....................................................................................................... 170
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
Overview ........................................................................................................................... 181
8.1.1
8.1.2
8.1.3
Register Descriptions......................................................................................................... 183
8.2.1
8.2.2
Sleep Mode........................................................................................................................ 187
8.3.1
8.3.2
8.3.3
Standby Mode.................................................................................................................... 188
Features ................................................................................................................ 149
Block Diagram ..................................................................................................... 150
Register Configuration ......................................................................................... 151
Break Address Register A (BARA)...................................................................... 152
Break Address Mask Register A (BAMRA) ........................................................ 153
Break Bus Cycle Register A (BBRA) .................................................................. 154
Break Address Register B (BARB) ...................................................................... 156
Break Address Mask Register B (BAMRB)......................................................... 157
Break Data Register B (BDRB) ........................................................................... 158
Break Data Mask Register B (BDMRB) .............................................................. 159
Break Bus Cycle Register B (BBRB)................................................................... 160
Break Control Register (BRCR)........................................................................... 162
Flow of the User Break Operation........................................................................ 170
Break on Instruction Fetch Cycle ......................................................................... 170
Break by Data Access Cycle ................................................................................ 171
Sequential Break .................................................................................................. 172
Value of Saved Program Counter......................................................................... 172
PC Trace............................................................................................................... 173
Usage Examples ................................................................................................... 174
Notes .................................................................................................................... 179
Power-Down Modes............................................................................................. 181
Pin Configuration ................................................................................................. 183
Register Configuration ......................................................................................... 183
Standby Control Register (STBCR) ..................................................................... 183
Standby Control Register 2 (STBCR2) ................................................................ 185
Transition to Sleep Mode ..................................................................................... 187
Canceling Sleep Mode.......................................................................................... 187
Precautions when Using the Sleep Mode ............................................................. 187
......................................................................................... 181
...................................................................................... 149