R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 122

IC R8C MCU FLASH 4K 20SSOP

R5F211B1SP#U0

Manufacturer Part Number
R5F211B1SP#U0
Description
IC R8C MCU FLASH 4K 20SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/1Br
Datasheets

Specifications of R5F211B1SP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
For Use With
R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F211B1SP#U0R5F211B1SP#V0
Manufacturer:
MICREL
Quantity:
2 860
R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 13.2
Option Function Select Register
Watchdog Timer Control Register
b7 b6 b5 b4
NOTES :
b7 b6 b5 b4
1.
2.
1 1 1
0 0
The OFS register is on the flash memory. Write to the OFS register w ith a program.
If the block including the OFS register is erased, FFh is set to the OFS register.
Dec 08, 2006
b3 b2 b1 b0
b3 b2 b1 b0
Registers OFS and WDC
1
Bit Symbol
Bit Symbol
CSPROINI
ROMCP1
WDTON
ROMCR
(b6-b4)
(b4-b0)
Symbol
Symbol
WDC7
WDC
OFS
(b1)
(b5)
(b6)
Page 104 of 315
Watchdog timer start
select bit
Reserved bit
ROM code protect
disabled bit
ROM code protect bit
Reserved bits
Count source protection
mode after reset select
bit
High-order bits of w atchdog timer
Reserved bit
Reserved bit
Prescaler select bit
(1)
Address
Bit Name
Address
Bit Name
0FFFFh
000Fh
0 : Starts w atchdog timer automatically after reset.
1 : Watchdog timer is inactive after reset.
Set to 1.
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
Set to 1.
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
Set to 0. When read, the content is undefined.
Set to 0.
0 : Divided by 16
1 : Divided by 128
Before Shipment
After Reset
00X11111b
Function
Function
FFh
(2)
13. Watchdog Timer
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO

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