R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 224

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.28
IIC bus Status Register
b7 b6 b5 b4
NOTES :
1.
2.
3.
4.
5.
6.
7.
Each bit is set to 0 by reading 1 bef ore writing 0.
This f lag is enabled in slav e receiv e mode of the I
When two or more master dev ices attempt to occupy the bus at nearly the same time, if the I2C bus Interf ace monitors the SDA pin
and the data which the I2C bus Interf ace transmits is dif f erent, the AL f lag is set to 1 and the bus is occupied by another master.
The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receiv e acknowledge bit is set to 1, transf er is
halted).
The RDRF bit is set to 0 when reading data f rom the ICDRR register.
Bits TEND and TDRE are set to 0 when writing data to the ICDRT register.
Ref er to 16.3.8.1 Accessing of Registers Associated with I
Dec 08, 2006
b3
b2 b1
ICSR Register
b0
Bit Symbol
Symbol
NACKF
STOP
RDRF
TEND
TDRE
(7)
ICSR
ADZ
AAS
AL
Page 206 of 315
General call address
recognition flag
Slave address recognition
flag
Arbitration lost flag /
overrun error flag
Stop condition detection
flag
No acknow ledge detection
flag
Receive data register
full
Transmit end
Transmit data empty
(1,5)
(1)
(1)
(1,4)
Address
Bit Name
00BCh
(1,6)
2
(1,2)
C bus f ormat.
(1)
(1,6)
2
C bus Interface f or more inf ormation.
When the general call address is detected , this flag
is set to 1.
This flag is set to 1 w hen the first frame follow ing
start condition matches bits SVA0 to SVA6 in the
SAR register in slave receive mode. (Detect the
slave address and generate call address.)
When the I2C bus format is used, this flag indicates
that arbitration has been lost in master mode. In the
follow ing cases, this flag is set to 1
This flag indicates an overrun error w hen the clock
synchronous format is used.
In the follow ing case, this flag is set to 1.
When the stop condition is detected after the frame
is transferred, this flag is set to 1.
When no ACKnow ledge is detected from receive
device after transmission, this flag is set to 1.
When receive data is transferred from registers
ICDRS to ICDRR, this flag is set to 1.
When the 9th clock cycle of the SCL signal in the I
bus format occurs w hile the TDRE bit is set to 1, this
flag is set to 1.
This flag is set to 1 w hen the final bit of the transmit
frame is transmitted in the clock synchronous format.
In the follow ing cases, this flag is set to 1.
• Data is transferred from registers ICDRT to ICDRS
• When setting the TRS bit in the ICCR1
• When generating the start condition
• When changing from slave receive mode to
• When the internal SDA signal and SDA pin
• When the start condition is detected and the
• When the last bit of the next data item is
and the ICDRT register is empty.
register to 1 (transmit mode).
(including retransmit).
slave transmit mode.
level do not match at the rise of the SCL signal
in master transmit mode.
SDA pin is held “H” in master transmit/receive
mode.
received w hile the RDRF bit is set to 1.
16. Clock Synchronous Serial Interface
After Reset
0000X000b
Function
(3)
.
2
C
RW
RW
RW
RW
RW
RW
RW
RW
RW