R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 244

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.45
16.3.6
Table 16.8
1Tcyc = 1/f1(s)
When setting the I
two cases:
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 16.45 shows the Timing of Bit Synchronization Circuit and Table 16.8 lists the Time between Changing
SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal.
• If the SCL signal is driven L level by a slave device
• If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Dec 08, 2006
Bit Synchronization Circuit
CKS3
0
1
Timing of Bit Synchronization Circuit
Monitoring of SCL Signal
Time between Changing SCL Signal from “L” Output to High-Impedance and
ICCR1 Register
Basis clock of SCL
2
C bus interface to master mode, the high-level period may become shorter in the following
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monitor timing
Internal SCL
SCL
CKS2
0
1
0
1
VIH
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
Time for Monitoring SCL
16. Clock Synchronous Serial Interface