R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 89

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 10.8
(flash memory operates)
(flash memory stops)
To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is
generated and the CPU clock supply is started.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
Wait mode
Figure 10.8 shows the Time from Wait Mode to Interrupt Routine Execution.
FMR0 Register
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
FMSTP Bit
Dec 08, 2006
0
1
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
Time from Wait Mode to Interrupt Routine Execution
Interrupt request generated
activation sequence
× 12 cycles + 30 µs (max.)
Time until Flash Memory
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Period of system clock
Period of system clock
Flash memory
is Activated (T1)
× 12 cycles
T1
CPU clock restart sequence
Time until CPU Clock
Period of CPU clock
is Supplied (T2)
Same as above
× 6 cycles
T2
Period of CPU clock
Time for Interrupt
Same as above
Sequence (T3)
× 20 cycles
Interrupt sequence
10. Clock Generation Circuit
Following total time is the
time from wait mode until
an interrupt routine is
executed.
T3
Remarks