R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 146

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
14.2.1
Table 14.7
NOTE:
Count sources
Count operations
Divide ratio
Count start condition
Count stop condition
Interrupt request
generation timing
TZOUT pin function
INT0 pin function
Read from timer
Write to timer
1. The IR bit in the TZIC register is set to 1 (interrupt requested) when writing to the TZPR or PREZ
In timer mode, a count source which is internally generated or timer X underflow is counted (refer to Table
14.7 Timer Mode Specifications). The TZSC register is not used in timer mode. Figure 14.16 shows Registers
TZMR and PUM in Timer Mode.
register while both of the following conditions are met.
Disable interrupts before writing to the TZPR or PREZ register in the above state.
• TZWC bit in TZMR register is set to 0 (write to reload register and counter simultaneously)
• TZS bit in TZMR register is set to 1 (count starts)
Dec 08, 2006
Item
Timer Mode
(1)
Timer Mode Specifications
Page 128 of 315
f1, f2, f8, Timer X underflow
• Decrement
• When the timer underflows, it reloads the reload register contents before the
1/(n+1)(m+1) fi: Count source frequency
n: Value set in PREZ register, m: value set in TZPR register
1 (count starts) is written to the TZS bit in the TZMR register.
0 (count stops) is written to the TZS bit in the TZMR register.
• When timer Z underflows [timer Z interrupt].
Programmable I/O port
Programmable I/O port, or INT0 interrupt input
The count value can be read out by reading registers TZPR and PREZ.
• When registers TZPR and PREZ are written while the count is stopped,
• When registers TZPR and PREZ are written during the count while the TZWC
count continues. (When timer Z underflows, the contents of timer Z primary
reload register is reloaded.)
values are written to both the reload register and counter.
bit is set to 0 (writing to the reload register and counter simultaneously), the
value is written to each reload register of registers TZPR and PREZ at the
following count source input, the data is transferred to the counter at the
second count source input, and the count re-starts at the third count source
input.
When the TZWC bit is set to 1 (writing to only the reload register), the value is
written to each reload register of registers TZPR and PREZ (the data is
transferred to the counter at the following reload).
Specification
14. Timers