R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 174

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 15.5
UARTi Transmit / Receive Control Register 0 (i = 0 or 1)
b7 b6 b5 b4
NOTE :
1.
If the BRG count source is sw itched, set the UiBRG register again.
Dec 08, 2006
b3 b2
0
Registers U0C0 to U1C0
b1 b0
Bit Symbol
UFORM
Symbol
CKPOL
TXEPT
U0C0
U1C0
CLK0
CLK1
NCH
(b2)
(b4)
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BRG count source select
bits
Reserved bit
Transmit register empty
flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Data output select bit
CLK polarity select bit
Transfer format select bit 0 : LSB first
(1)
Address
Bit Name
00A4h
00ACh
b1 b0
0 0 : Selects f1.
0 1 : Selects f8.
1 0 : Selects f32.
1 1 : Do not set.
Set to 0.
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
0 : TXDi pin is for CMOS output.
1 : TXDi pin is for N-channel open drain output.
0 : Transmit data is output at falling edge of transfer
1 : Transmit data is output at rising edge of transfer
1 : MSB first
clock and receive data is input at rising edge.
clock and receive data is input at falling edge.
After Reset
Function
08h
08h
15. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RO
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