R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 133

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 14.6
14.1.3
Table 14.4
Count source
Count operations
Divide ratio
Count start condition
Count stop condition
Interrupt request
generation timing
INT10/CNTR00,
INT11/CNTR01
pin functions
CNTR0 pin function
Read from timer
Write to timer
Select functions
Timer X Mode Register
b7 b6 b5 b4
NOTES :
0 0 0 0
1.
2.
In event counter mode, external signal inputs to the INT1/CNTR0 pin are counted (refer to Table 14.4 Event
Counter Mode Specifications). Figure 14.6 shows the TXMR Register in Event Counter Mode.
The IR bit in the INT1IC register may be set to 1 (requests interrupt) w hen the R0EDG bit is rew ritten.
Refer to 12.5.5 Changing Interrupt Sources.
Refer to 14.1.6 Notes on Tim er X for precautions regarding the TXS bit.
Dec 08, 2006
Item
Event Counter Mode
b3 b2
Event Counter Mode Specifications
TXMR Register in Event Counter Mode
b1
1
b0
0
Bit Symbol
TXMOD0
TXMOD1
TXOCNT
TXMOD2
Symbol
R0EDG
TXEDG
TXUND
TXMR
TXS
Page 115 of 315
External signal which is input to CNTR0 pin (Active edge selectable by software)
• Decrement
• When the timer underflows, the contents of the reload register are reloaded and
1/(n+1)(m+1) n: value set in PREX register, m: value set in TX register
1 (count starts) is written to the TXS bit in the TXMR register.
0 (count stops) is written to the TXS bit in the TXMR register.
• When timer X underflows [timer X interrupt]
Count source input (INT1 interrupt input)
Programmable I/O port
The count value can be read out by reading registers TX and PREX.
• When registers TX and PREX are written while the count is stopped, values are
• When registers TX and PREX are written during the count, the value is written
• INT1/CNTR0 signal polarity switch function
• Count source input pin select function
the count is continued.
written to both the reload register and counter.
to each reload register of registers TX and PREX at the following count source
input, the data is transferred to the counter at the second count source input,
and the count re-starts at the third count source input.
The R0EDG bit can select the active edge of the count source.
The CNTRSEL bit in the UCON register can select the CNTR00 or CNTR01
pin.
Operating mode select bits 0, 1
_____
INT1
Timer X count start flag
Set to 0 in event counter mode.
Set to 0 in event counter mode.
Set to 0 in event counter mode.
Set to 0 in event counter mode.
polarity sw itch bit
/CNTR0 signal
Address
Bit Name
008Bh
(1)
(2)
Specification
b1 b0
1 0 : Event counter mode
0 : Rising edge
1 : Falling edge
0 : Stops counting.
1 : Starts counting.
After Reset
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW