R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 274

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 18.6
Flash Memory Control Register 1
b7 b6 b5 b4
NOTES :
1
1.
2.
3.
To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode
enable) . Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled).
When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.
To set this bit to 0, set it to 0 immediately after setting it first to 1.
To set this bit to 1, set it to 1.
Dec 08, 2006
0
b3 b2
0
0
b1 b0
FMR1 Register
Bit Symbol
(b4-b2)
Symbol
FMR15
FMR16
FMR11
FMR1
(b0)
(b7)
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—
—
—
Reserved bit
EW1 mode select bit
Reserved bits
Block 0 rew rite disable bit
Block 1 rew rite disable bit
Reserved bit
Address
Bit Name
01B5h
(1, 2)
(2,3)
(2,3)
When read, the content is undefined.
0 : EW0 mode
1 : EW1 mode
Set to 0.
0 : Enables rew rite.
1 : Disables rew rite.
0 : Enables rew rite.
1 : Disables rew rite.
Set to 1.
After Reset
1000000Xb
Function
18. Flash Memory
RW
RW
RW
RW
RW
RW
RO