R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 101

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 12.3
12.1.6
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
2.
3.
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 12.3 shows the Interrupt Control Register and Figure 12.4 shows the INT0IC Register
Only 0 can be w ritten to the IR bit. Do not w rite 1.
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.5.6 Changing Interrupt Control Registers.
The IICSEL bit in the PMR register sw itches functions.
Dec 08, 2006
Interrupt Control
Interrupt Control Register
Bit Symbol
(b7-b4)
ILVL0
ILVL1
ILVL2
KUPIC
ADIC
SSUAIC/IIC2AIC
CMP1IC
S0TIC, S1TIC
S0RIC, S1RIC
TXIC
TZIC
INT1IC
INT3IC
TCIC
CMP0IC
Page 83 of 315
—
IR
(2)
Symbol
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
(3)
Bit Name
0051h, 0053h
0052h, 0054h
Address
005Ah
004Dh
004Eh
004Fh
0050h
0056h
0058h
0059h
005Bh
005Ch
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt
1 : Requests interrupt
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
After Reset
Function
12. Interrupts
RW
RW
RW
RW
RW
—
(1)