R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 206

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.16
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Dec 08, 2006
SSCRH register
SSCRH register
SSER register
Mode)
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Read receive data in SSRDR register
Read receive data in SSRDR register
Read ORER bit in SSSR register
Read ORER bit in SSSR register
Read RDRF bit in SSSR register
Dummy read of SSRDR register
Read RDRF in SSSR register
No
No
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ORER = 1 ?
ORER = 1 ?
Initialization
RDRF = 1 ?
RDRF = 1 ?
received?
Last data
Start
End
RSSTP bit ← 1
RSSTP bit ← 0
RE bit ← 0
No
No
Yes
No
Yes
Yes
Yes
Yes
processing
Overrun
error
(3) If a receive error occurs, perform error.
(6) Processing after reading the ORER bit. Then set
(1) After setting each register in the clock synchronous
(2) Determine whether it is the last 1 byte of data to be
(4) Confirm that the RDRF bit is set to 1. If the RDRF
(5)Before the last 1 byte of data is received, set the
(7) Confirm that the RDRF bit is set to 1. When the
RSSTP bit to 1 and stop after the data is
received.
the ORER bit to 0. Transmission/reception cannot
be restarted while the ORER bit is set to 1.
serial I/O with chip select register, a dummy read of
the SSRDR register is performed and the receive
operation is started.
received. If so, set to stop after the data is received.
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1 byte
of data. If the SSRDR register is read before setting
the RE bit to 0, the receive operation is restarted
again.
16. Clock Synchronous Serial Interface