R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 91

IC R8C MCU FLASH 4K 20SSOP

R5F211B1SP#U0

Manufacturer Part Number
R5F211B1SP#U0
Description
IC R8C MCU FLASH 4K 20SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/1Br
Datasheets

Specifications of R5F211B1SP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
For Use With
R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F211B1SP#U0R5F211B1SP#V0
Manufacturer:
MICREL
Quantity:
2 860
R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 10.9
Figure 10.10
medium-speed mode
High-speed mode,
(flash memory operates)
mode
Interrupt
request
generated
Stop
(flash memory stops)
Figure 10.10 shows the State Transitions in Power Control.
Interrupt
OCD2 = 0
CM05 = 0
CM13 = 1
FMR0 Register
Dec 08, 2006
FMSTP Bit
Internal power
stability time
Wait mode
0
1
150 µs
(max.)
State Transitions in Power Control
Time from Stop Mode to Interrupt Routine Execution
T0
WAIT
instruction
Oscillation time of
CPU clock source
used immediately
before stop mode
Page 73 of 315
× 12 cycles + 30 µs (max.)
Time until Flash Memory
Low-speed on-chip
Period of system clock
Period of system clock
High-speed on-chip
oscillator mode
oscillator mode
is Activated (T2)
HRA01 = 0
HRA01 = 1
HRA00 = 1
T1
OCD2 = 1
CM14 = 0
OCD2 = 1
Reset
× 12 cycles
Interrupt
activation sequence
Flash memory
Stop mode
Time until CPU Clock
Period of CPU clock
T2
is Supplied (T3)
Same as above
× 6 cycles
CM10 = 1
(
all oscillators stop
CPU clock restart
sequence
Period of CPU clock
Time for Interrupt
T3
)
Same as above
Sequence (T4)
× 20 cycles
There are six power control modes.
CM05: Bit in CM0 register
CM10, CM13, CM14: Bit in CM1 register
OCD2: Bit in OCD register
HRA00, HRA01: Bit in HRA0 register
(1) High-speed mode
(2) Medium-speed mode
(3) High-speed on-chip oscillator mode
(4) Low-speed on-chip oscillator mode
(5) Wait mode
(6) Stop mode
Interrupt sequence
10. Clock Generation Circuit
Following total time is
the time from stop
mode until an interrupt
handling is executed.
T4
Remarks

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