R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 268

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 18.4
18.3.2
Option Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
2.
1 1 1
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the
OFS register in parallel I/O mode. Figure 18.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
The OFS register is on the flash memory. Write to the OFS register w ith a program.
If the block including the OFS register is erased, FFh is set to the OFS register.
Dec 08, 2006
ROM Code Protect Function
OFS Register
1
Bit Symbol
CSPROINI
ROMCP1
WDTON
ROMCR
(b6-b4)
Symbol
OFS
(b1)
Page 250 of 315
—
—
Watchdog timer start
select bit
Reserved bit
ROM code protect
disabled bit
ROM code protect bit
Reserved bits
Count source protect
mode after reset select
bit
(1)
Address
Bit Name
0FFFFh
0 : Starts w atchdog timer automatically after reset.
1 : Watchdog timer is inactive after reset.
Set to 1.
0 : ROM code protect disabled
1 : ROMCP1enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
Set to 1.
0 : Count source protect mode enabled after reset.
1 : Count source protect mode disabled after reset.
Before Shipment
Function
FFh
(2)
18. Flash Memory
RW
RW
RW
RW
RW
RW
RW