R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 241

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.42
16.3.4.2
In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the
transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when
the MST bit is set to 0.
Figure 16.42 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
(2) The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the
(3) Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1 by
ICDRT register
ICDRS register
ICCR1 register
Dec 08, 2006
ICSR register
by program
Processing
TDRE bit in
TRS bit in
(output)
ICCR1 register and set the MST bit (initial setting).
ICCR1 register to 1.
writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1. Continuous
transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. When
switching from transmit to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
SDA
SCL
Transmit Operation
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
(2) Set TRS bit to 1
1
0
1
0
(3) Data write to
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ICDRT register
Data 1
b0
Data 1
1
b1
(3) Data write to
2
ICDRT register
b6
Data 2
7
b7
8
b0
Data 2
1
16. Clock Synchronous Serial Interface
(3) Data write to
ICDRT register
b6
7
b7
8
(3) Data write to
Data 3
Data 3
ICDRT register
b0
1