R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 242

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.43
16.3.4.3
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 16.43 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.
ICDRR register
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
(2) The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being
(3) Data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1,
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
ICDRS register
ICCR1 register
ICCR1 register
Dec 08, 2006
ICSR register
by program
Processing
RDRF bit in
MST bit in
TRS bit in
ICCR1 register and set the MST bit (initial setting).
output.
when the receive operation is completed. Since the next byte of data is enabled when the MST bit is set
to 1, the clock is output continuously. Continuous reception is enabled by reading the ICDRR register
every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock cycle while the
RDRF bit is set to 1, and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
operation) and read the ICDRR register. The SCL signal is fixed “H” after reception of the following
byte of data is completed.
(input)
SDA
SCL
Receive Operation
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
1
0
1
0
1
0
(2) Set MST bit to 1
(when transfer clock is output)
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b0
1
b1
Data 1
2
(3) Read ICDRR register
b6
7
b7
8
b0
Data 1
1
16. Clock Synchronous Serial Interface
Data 2
b6
7
(3) Read ICDRR register
b7
8
Data 2
1
b0
Data 3
2