R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 80

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 10.4
Oscillation Stop Detection Register
b7 b6 b5 b4
NOTES :
0 0 0 0
1.
2.
3.
4.
5.
6.
7.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to this register.
The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a main clock oscillation stop is detected
w hile bits OCD1 to OCD0 are set to 11b (oscillation stop detection function enabled). If the OCD3 bit is set to 1 (main
clock stops), the OCD2 bit remains unchanged even w hen set to 0 (main clock selected).
The OCD3 bit is enabled w hen bits OCD1 to OCD0 are set to 11b (oscillation stop detection function
enabled).
Set bits OCD1 to OCD0 to 00b (oscillation stop detection function disabled) before entering stop or
on-chip oscillator mode (main clock stops).
The OCD3 bit remains 0 (main clock oscillates) if bits OCD1 to OCD0 are set to 00b.
The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
Refer to Figure 10.8 Sw itching Clock Source from Low -speed On-Chip Oscillator to Main Clock for the
sw itching procedure w hen the main clock re-oscillates after detecting an oscillation stop.
Dec 08, 2006
b3 b2 b1 b0
OCD Register
Bit Symbol
(b7-b4)
Symbol
OCD0
OCD1
OCD2
OCD3
OCD
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—
Oscillation stop detection enable
bits
System clock select bit
Clock monitor bit
Reserved bits
(1)
Address
Bit Name
000Ch
(3,5)
(6)
b1 b0
0 0 : Oscillation stop detection function
0 1 : Do not set.
1 0 : Do not set.
1 1 : Oscillation stop detection function
0 : Selects main clock.
1 : Selects on-chip oscillator clock.
0 : Main clock oscillates.
1 : Main clock stops.
Set to 0.
disabled
enabled
(4,7)
After Reset
Function
04h
(7)
10. Clock Generation Circuit
(2)
RW
RW
RW
RW
RW
RO