R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 245

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.46
16.3.7
Figures 16.46 to 16.49 show Examples of Register Setting When Using I
Dec 08, 2006
Examples of Register Setting
Example of Register Setting in Master Transmit Mode (I
ICCR1 register
ICCR2 register
ICSR register
ICSR register
ICCR2 register
ICCR1 register
ICSR register
Read STOP bit in ICSR register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Read ACKBR bit in ICIER register
Read BBSY bit in ICCR2 register
Read TEND bit in ICSR register
Read TDRE bit in ICSR register
Read TEND bit in ICSR register
No
No
Page 227 of 315
No
No
No
No
ACKBR = 0 ?
Initial setting
BBSY = 0 ?
Yes
TEND = 1 ?
TDRE = 1 ?
TEND = 1 ?
Last byte ?
STOP = 1 ?
Transmit
mode ?
TEND bit ← 0
STOP bit ← 0
TDRE bit ← 0
BBSY bit ← 1
BBSY bit ← 0
Start
MST bit ← 1
MST bit ← 0
TRS bit ← 1
SCP bit ← 0
SCP bit ← 0
TRS bit ← 0
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Master receive
mode
• Set the STOP bit in the ICSR register to 0.
• Set the IICSEL bit in the PMR register to 1.
(1) Judge the state of the SCL and SDA lines.
(2) Set to master transmit mode.
(3) Generate the start condition.
(4) Set the transmit data of the 1st byte
(5) Wait for 1 byte to be transmitted.
(6) Judge the ACKBR bit from the specified slave device.
(7) Set the transmit data after 2nd byte (except the last byte).
(8) Wait until the ICRDT register is empty.
(9) Set the transmit data of the last byte.
(10) Wait for end of transmission of the last byte.
(11) Set the TEND bit to 0.
(12) Set the STOP bit to 0.
(13) Generate the stop condition.
(14) Wait until the stop condition is generated.
(15) Set to slave receive mode
(slave address + R/W).
Set the TDRE bit to 0.
16. Clock Synchronous Serial Interface
2
C bus interface.
2
C bus Interface Mode)